The present invention relates to a data transfer control system for controlling a data request to a higher-rank CPU for transfer of write data from the higher-rank CPU by means of packet communication or the like to a lower-rank information recording sub-system connected to a higher-rank apparatus, such as the higher-rank CPU or the like.
A communication control unit, such as an optical communication control unit or the like, used in such a lower-rank information recording sub-system, includes a buffer for accommodating a difference in transfer speed between a higher-rank CPU and a lower-rank memory unit. The communication control unit requests the higher-rank CPU to send data according to the size or capacity of the buffer for control of writing. Once a request for data transfer to the buffer is sent, further data request is stopped and the communication control unit waits until the data for one request is delivered from the buffer to a lower-rank memory unit provided at a lower-rank position. When the data for one request has been delivered, the communication control unit transmits a data request to the higher-rank CPU again. The communication control unit controls the data transfer from the higher-rank CPU to the lower-rank memory unit by repetition of the above operation. A conventional data transfer control system described above is disclosed in JP-A-4-225452.
With such a conventional system, however, as the length of the communication cable for connecting the higher-rank CPU and the information recording sub-system is made longer, eventually the time from issuance of the data request to the higher-rank CPU to the data arrival time of the data in the information recording sub-system will exceed the time it takes for the buffer to deliver all of its data in the full state. In the request for transfer of data to the buffer, even if a next data request is sent out immediately after data requested by a previous request has reached the buffer, the delivering of the received data to the lower-rank memory unit from the buffer will be completed before the next data is received from the higher-rank CPU. Accordingly, an empty state of the buffer occurs, and the data transfer to the lower-rank memory unit is interrupted during the empty state of the buffer, so that the buffer is not used efficiently.